? 2005 fairchild semiconductor corporation ds500414 www.fairchildsemi.com march 2001 revised january 2005 sstv16859 dual output 13-bit register with sstl-2 compatible i/o and reset sstv16859 dual output 13-bit register with sstl-2 compatible i/o and reset general description the sstv16859 is a dual output 13-bit register designed for use with 184 and 232 pin ddr-1 memory modules. the device has a differential input clock, sstl-2 compatible data inputs and a lvcmos compatible reset input. the device has been designed to meet the jedec ddr mod- ule register specifications. the device has been fabricated on an advanced sub- micron cmos process and is designed to operate at power supplies of less than 3.6v?s. features compliant with ddr-i registered module specifications operates at 2.5v 0.2v v dd sstl-2 compatible input structure sstl-2 compliant output structure differential sstl-2 compatible clock inputs low power mode when device is reset industry standard 64 pin tssop package also packaged in plastic fine-pitch ball grid array (fbga) ordering code: note 1: ordering code ? g ? indicates trays. note 2: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. order number package number package description sstv16859g (note 1)(note 2) bga96a 96-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide sstv16859mtd (note 2) mtd64 64-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 sstv16859 connection diagrams pin assignment for tssop pin assignment for fbga (top thru view) pin descriptions fbga pin assignments truth table l = logic low h = logic high x = don ? t care but not floating unless noted = low-to-high clock transition = high-to-low clock transition q n-1 = output remains in previously clocked state pin name description q 1a -q 13a sstl-2 compatible register outputs q 1b -q 13b d 1 -d 13 sstl-2 compatible register inputs reset asynchronous lvcmos reset input ck positive master clock input ck negative master clock input v ref voltage reference pin for sstl level inputs v ddq power supply voltage for output signals v dd power supply voltage for inputs nc electrically isolated no connect 12345 6 a nc nc nc nc nc nc b q 12a q 13a gnd gnd nc nc c q 10a q 11a gnd gnd nc nc d q 8a q 9a v ddq v ddq d 13 d 12 e q 6a q 7a v ddq v dd d 11 d 10 f q 4a q 5a v ddq v dd d 9 d 8 g q 2a q 3a gnd gnd d 7 reset h q 1a q 13b gnd gnd nc ck j q 12b q 11b gnd v ref nc ck k q 10b q 9b v ddq v dd nc nc l q 8b q 7b v ddq v dd d 5 d 6 m q 6b q 5b v ddq v ddq d 3 d 4 n q 4b q 3b gnd gnd d 1 d 2 p q 2b q 1b gnd gnd nc nc r nc nc nc nc nc nc t nc nc nc nc nc nc reset d n ck ck q n l x or floating x or floating x or floating l hl l hh h hxlhq n-1 hxhlq n-1
3 www.fairchildsemi.com sstv16859 functional description the sstv16859 is a 13-bit dual register with sstl-2 com- patible inputs and outputs. input data is transferred to out- put data on the rising edge of the differential clock pair. when the reset signal is asserted low all outputs are placed into the low logic state and all input comparators are disabled for power savings. output glitches are pre- vented by disabling the internal registers more quickly than the input comparators. when reset is removed, the sys- tem designer must insure the clock and data inputs to the device are stable during the rising transition of the reset signal. the sstl-2 data inputs transition based on the value of v ref . v ref is a stable system reference used for setting the trip point of the input buffers of the sstv16859 and other sstl-2 compatible devices. the reset signal is a standard cmos compatible input and is not referenced to the v ref signal. logic diagram for n = 1 to 13
www.fairchildsemi.com 4 sstv16859 absolute maximum ratings (note 3) recommended operating conditions (note 5) note 3: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the ? electrical characteristics ? table are not guaranteed at the absolute maximum ratings. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 4: io absolute maximum rating must be observed. note 5: the reset input of the device must be held at v dd or gnd to ensure proper device operation. the differential inputs must not be floating, unless reset is asserted low. dc electrical characteristics (2.3v v dd 2.7v) supply voltage (v ddq ) ? 0.5v to + 3.6v supply voltage (v dd ) ? 0.5v to + 3.6v reference voltage (v ref ) ? 0.5v to + 3.6v input voltage (v i ) ? 0.5v to v dd + 0.5v output voltage (v o ) outputs active (note 4) ? 0.5v to v ddq + 0.5v dc input diode current (i ik ) v i < 0v ? 50 ma v i > v dd + 50 ma dc output diode current (i ok ) v o < 0v ? 50 ma v o > v ddq + 50 ma dc output source/sink current (i oh /i ol ) 50 ma dc v dd or ground current per supply pin (i dd or ground) 100 ma storage temperature range (t stg ) ? 65 c to + 150 c esd (human body model) 7000v power supply (v ddq ) 2.3v to 2.7v power supply (v dd ) operating range v ddq to 2.7v reference supply (v ref = v ddq /2) 1.15 to 1.35 termination voltage (v tt )v ref 40 mv input voltage 0 to v dd output voltage (v o ) output in active states 0v to v ddq output current i oh /i ol v dd = 2.3v to 2.7v 20 ma free air operating temperature (t a )0 c to + 70 c symbol parameter conditions v dd min typ max units (v) v ikl input low clamp voltage i i = ? 18 ma 2.3 ? 1.2 v v ikh input high clamp voltage i i = + 18 ma 2.3 3.5 v v ih-ac ac high level input voltage data inputs v ref + 310mv v v il-ac ac low level input voltage data inputs v ref ? 310mv v v ih-dc dc high level input voltage data inputs v ref + 150mv v v il-dc dc low level input voltage data inputs v ref ? 150mv v v ih high level input voltage reset 1.7 v v il low level input voltage reset 0.7 v v icr common mode input voltage range ck, ck 0.97 1.53 v v i(pp) peak to peak input voltage ck, ck 360 mv v oh high level output voltage i oh = ? 100 a 2.3 to 2.7 v dd ? 0.2 v i oh = ? 16 ma 2.3 1.95 v ol low level output voltage i ol = 100 a 2.3 to 2.7 0.2 v i ol = 16 ma 2.3 0.35 i i input leakage current v i = v dd or gnd 2.7 5.0 a i dd static standby reset = gnd, i o = 0 2.7 10 a static operating reset = v dd , i o = 0 25 ma v i = v ih(ac) or v il(ac) i ddd dynamic operating current reset = v dd , i o = 0 2.7 a/mhz clock only v i = v ih(ac) or v il(ac) 120 ck, ck duty cycle 50% dynamic operating current reset = v dd , i o = 0 a/mhz per data input v i = v ih(ac) or v il(ac) ck, ck duty cycle 50% 15 data input = ? clock rate 50% duty cycle
5 www.fairchildsemi.com sstv16859 dc electrical characteristics (continued) ac electrical characteristics (note 6) note 6: refer to figure 1 through figure 7. note 7: this parameter is not production tested. note 8: for data signal input slew rate 1 v/ns. note 9: for data signal input slew rate 0.5 v/ns and < 1 v/ns. note 10: for ck, ck signals input slew rates are 1 v/ns. capacitance (note 11) note 11: t a = + 25 c, f = 1 mhz, capacitance is characterized but not tested. symbol parameter conditions v dd min typ max units (v) r oh output high on resistance i oh = ? 20 ma 2.3 to 2.7 7 20 ? r ol output low on resistance i ol = 20 ma 2.3 to 2.7 7 20 ? r o ? | r oh - r ol |i o = 20 ma, t a = 25 c2.5 4 ? symbol parameter t a = 0 c to + 70 c, c l = 30 pf, r l = 50 ? units v dd = 2.5v 0.2v; v ddq = 2.5v 0.2v min typ max f max maximum clock frequency 200 mhz t w pulse duration, ck, ck high or low (figure 2) 2.5 ns t act differential inputs activation time, 22 ns (note 7) data inputs must be low after reset high (figure 3) t inact differential inputs de-activation time, 22 ns (note 7) data and clock inputs must be held at valid levels (not floating) after reset low t s setup time, fast slew rate (note 8)(note 9) (figure 5) 0.75 ns setup time, slow slew rate (note 9)(note 10) (figure 5) 0.9 t h hold time, fast slew rate (note 8)(note 10) (figure 5) 0.75 ns hold time, slow slew rate (note 9)(note 10) (figure 5) 0.9 t rem reset removal time (figure 7) 10 ns t phl , t plh propagation delay ck, ck to q n (figure 4) 1.1 2.8 ns t phl propagation delay reset to q n (figure 6) 5.0 ns symbol parameter min typ max units conditions c in data pin input capacitance 2.2 3.2 pf v dd = 2.5v, v i = v ref 310 mv ck, ck - input capacitance 2.2 3.2 pf v dd = 2.5v, v icr = 1.25, v i(pp) = 360 mv reset 2.3 3.3 pf v dd = 2.5v, v i = v dd or gnd
www.fairchildsemi.com 6 sstv16859 ac loading and waveforms (see notes a through f below) note: c l includes probe and jog capacitance figure 1. ac test circuit figure 2. voltage waveforms - pulse duration note: i dd tested with clock and data inputs held at v dd or gnd, and i o = 0 ma. figure 3. voltage and current waveforms inputs active and inactive times figure 4. voltage waveforms - propagation delay times figure 5. voltage waveforms - setup and hold times figure 6. voltage waveforms - reset propagation delay times figure 7. voltage waveforms - reset removal delay times note a: all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z 0 = 50 ? , input slew rate = 1v/ns 20% (unless otherwise specified). note b : the outputs are measured one at a time with one transition per measurement. note c: v tt = v ref = v dd /2. note d: v ih = v ref + 310 mv (ac voltage levels) for differ- ential inputs. v ih = v dd for lvcmos input. note e: v il = v ref ? 310 mv (ac voltage levels) for differ- ential inputs. v il = gnd for lvcmos input. note f: removal time (t rem ) is tested with one data input held active high. the propagation time from ck to the cor- responding output must meet valid timing specifications for the measurement to be accurate.
7 www.fairchildsemi.com sstv16859 physical dimensions inches (millimeters) unless otherwise noted 96-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga96a
www.fairchildsemi.com 8 sstv16859 dual output 13-bit register with sstl-2 compatible i/o and reset physical dimensions inches (millimeters) unless otherwise noted (continued) 64-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd64 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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